1. Field of the Invention
This invention relates to the semiconductor processing and, more particularly, to a method for planarizing an interlevel dielectric using a two step chemical-mechanical polish (CMP).
2. Description of the Relevant Art
Semiconductor devices formed into semiconductor substrates are generally well known. The densities of semiconductor devices have steadily increased over the years. Operating speed has increased as a result of a reduction in geometries of individual semiconductor devices. As device geometries drop below 2.0 .mu.m per side, however, the marginal benefit of further device geometry reductions is limited by the size of interconnect contacts. Accordingly, circuit designers are turning towards multiple level interconnects to increase the density of their devices. Semiconductor processes employing one and two levels of interconnect are now well known to those skilled in semiconductor manufacturing and process development. More recently, however, state-of-the-art processes are beginning to employ three, four and five levels of interconnect. As the number of vertical levels increases, the importance of adequately planarizing each interlevel dielectric (i.e., dielectric material placed between levels of interconnect) increases as well.
Planarization refers to the technique used for producing a substantially flat or "planar" topographical surface from a pre-existing non-planar surface. The degree of planarity varies with the planarization process chosen. Photolithography, etch, and deposition steps all require a surface which is as planar as possible. When vertical interconnect levels are added to a process, planarization steps must be incorporated in the process to ensure that each interlevel dielectric is as planar as possible, in readiness for the subsequent interconnect level.
There are many types of planarization processes. A popular reflow process is typically used in processes embodying less dense features. Reflow entails depositing, for example, a borophosphosilicate glass (BPSG). Thereafter, the BPSG is heated such that it reflows across the topography to form a more planar surface than the initial surface. BPSG reflow however became increasingly ineffective as device features became increasing smaller. Accordingly, BPSG has given way to some extent to etchback process. Etchback involves depositing a photoresist layer onto the surface of the semiconductor. Photoresist is typically spin-on deposited to achieve a substantially level resist surface. Thereafter, the photoresist and underlying dielectric is etched at typically the same etch rate to preserve the planar topography of the removed resist within the dielectric.
Chemical-mechanical polish is a relatively recent advance in planarization technology. CMP has proved successful in planarizing either a dielectric or metal surface. In a CMP process, a semiconductor wafer is held in a wafer carrier and placed in contact with a chemical-mechanical polish pad attached to a CMP platen. The platen rotates with respect to the wafer and a chemical-mechanical slurry is introduced onto the polish platen surface. In a typical CMP slurry used to polish dielectrics such as oxide, silica particles are combined in a basic solution to effect a combination chemical and mechanical etch. The solution essentially provides the chemical etch component of the CMP, while the silica particles contribute to the mechanical abrasion and removal component. An acidic slurry solution containing an alumina abrasive is commonly used to polish metals such as tungsten.
Non-planar semiconductor surfaces are comprised of elevational high spots (hereinafter "peaks") and elevational low spots (hereinafter "valleys"). A step occurs between a peak and a valley. The step height can be quite severe if the peak and valley elevational disparity is large. In many instances, interlevel dielectrics incur elevational disparities in the range between 0.1 to 1.5 .mu.m during deposition. Accordingly, a need arises to remove those disparities, preferably using a CMP process. The effectiveness by which the disparities are reduced, if not removed, is referred to as a planarization factor. It is desirable that an elevational disparity of less than 0.01 .mu.m be achieved globally across the entire topography to ensure optimal processing of subsequent layers.
Planarization factor is dependent upon, for example, polish pad composition, force applied to the wafer against the polish pad, and the composition of the slurry. A polish pad can be either rigid or soft, with varying degrees of rigidity in between. The dielectric is one defined as having peaks and valleys, wherein the distance between densely spaced peaks is less than 10.0 .mu.m. and the distance between sparsely spaced peaks is greater than 10.0 .mu.m.
Rigid polish pads are desirable because rigid pads tend not to conform to the topography of the underlying wafer surface. A rigid pad will demonstrate a propensity to etch the peaks at a greater rate than the valleys because the rigid pad will predominantly contact only the peaks, leaving the valleys intact. Because of their rigidity, however, the rigid pads tend to create wafer "chatter". Wafer chatter refers to the effect caused by a rigid pad's inability to conform to the wafer surface at the leading and trailing edges of wafer surface peaks. The leading and trailing edges are defined as the corners of the respective peaks measured in the direction taken by the spinning pad. The leading edge, therefore, is the peak edge facing the incoming pad surface, whereas the trailing edge is the edge facing the outgoing pad surface. Chatter is demonstrated as a on/off (or contact/separation) of the pad to the wafer surface. The on/off or bounce experienced by the pad surface upon the peaks tends to dislodge large pieces of leading or trailing edge regions from the dielectric. The large fracture material thereafter moves with the pad, possibly causing abrasion of valley areas, or extensive removal of peak areas, as well as mechanical damage or scratches to the layer begin polished.
To avoid the effects of wafer chatter, softer (or more flexible) polish pads are frequently employed. Soft polish pads tend to conform to the sharpness at the leading and trailing edges to not only maintain contact with those edges, but also to smooth those edges in readiness for subsequent processing. Accordingly, soft pads used in lieu of rigid pads avoid wafer chatter problems. As the force applied to the wafer increases, soft pads tend, unfortunately, to make greater physical contact with the valley areas. Any contact with the valleys between sparsely spaced peaks result in lessened global planarization. Unfortunately, soft pads have a greater tendency to conform to valleys between sparsely spaced peaks rather than between densely spaced peaks.
It is therefore important to control the rigidity of the pad applied to the wafer surface. Along with selecting the right pad, it is also important to select the proper slurry characteristics. Low viscosity (i.e., low solid concentration) slurries generally demonstrate a greater flow or transfer rate of silica particles across the wafer. Typically, a low viscosity slurry will allow silica to move from areas of high contact pressure to areas of low contact pressure. High contact pressure areas are found at the peaks; low contact pressure areas are found at the valleys. A low viscosity CMP slurry results in significant material turnover and exchange in peak areas to valley areas, possibly causing chemical attack in valleys absent mechanical contact. Any appreciable etching of the valleys severely limits the overall CMP planarization. Slurry pH is also important in setting the chemical to mechanical removal rate ratio with higher pH giving a higher chemical removal rate for oxides.